Post Moore’s Law Computing
Chairs: Mark Hill and Kathy Yelick
University of Wisconsin, Madison
Mark Hill Website
Mark D. Hill is the Gene M. Amdahl Professor of Computer Sciences and Electrical & Computer Engineering at the University of Wisconsin–Madison, where he also co-leads the Wisconsin Multifacet project with David Wood. His research interests include parallel computer system design, memory system design, computer simulation, deterministic replay and transactional memory. He earned a PhD from University of California, Berkeley. He is an ACM Fellow and a Fellow of the IEEE.
University of California at Berkeley
Kathy Yelick Website
Katherine Yelick is a Professor of Electrical Engineering and Computer Sciences at the University of California at Berkeley and is also the Associate Laboratory Director for Computing Sciences at Lawrence Berkeley National Laboratory. She is the co-author of two books and more than 100 refereed technical papers on parallel languages, compilers, algorithms, libraries, architecture, and storage. She co-invented the UPC and Titanium languages and demonstrated their applicability across architectures through the use of novel runtime and compilation methods. She also co-developed techniques for self-tuning numerical libraries, including the first self-tuned library for sparse matrix kernels which automatically adapts the code to properties of the matrix structure and machine. Her work includes performance analysis and modeling as well as optimization techniques for memory hierarchies, multicore processors, communication libraries, and processor accelerators. She has worked with interdisciplinary teams on application scaling, and her own applications work includes parallelization of a model for blood flow in the heart. She earned her Ph.D. in Electrical Engineering and Computer Science from MIT and has been a professor of Electrical Engineering and Computer Sciences at UC Berkeley since 1991 with a joint research appointment at Berkeley Lab since 1996. She has received multiple research and teaching awards and is a member of the California Council on Science and Technology and a member of the National Academies committee on Sustaining Growth in Computing Performance.
Georgia Institute of Technology
Tom Conte Website
Tom Conte is a native of Delaware , but served his time in a corn field in the middle of Illinois, escaping only when he received his Ph.D. from the University of Illinois at Urbana-Champaign in 1992. From 1992-1995, he was an Assistant Professor at the University of South Carolina in Columbia, SC, where he met his wife (which was just about the only good thing that happened to him in South Carolina).
In 1995, Conte moved to NC State University (in Raleigh, NC), where he was an Assistant Professor (1995-1998), then an Associate Professor (1998-2002), and then an adjective-free Professor of Electrical and Computer Engineering . Somewhere in there (2000-2001) he took a short detour to DSP startup BOPS, inc. to serve as a manager of their back and compiler group and “Chief Microarchitect” (because they already had a “Chief Architect”). After cursing Computer Science as a faux discipline for decades, he accidentally became a professor of Computer Science at Georgia Tech, where he suffers to this day.
Conte currently directs a bunch of Ph.D. students in topics ranging from compiler design to advanced microarchitectures. His research is or has been supported by DARPA, Compaq (formerly Digital), Hewlett-Packard (formerly Compaq), IBM, Intel, TI, Sun, NASA, and the National Science Foundation.
The Post Moore’s Law Computing (PMLC) task force operated between 2017 and 2018, and led activities to address the future of computing as we reach the limit of Moore’s Law – the observable trend that the number of transistors per square inch on integrated circuits had doubled every year since their invention, leading to advancements in digital electronics. In order to move past the era of Moore’s law, new computational tools and systems must be developed. The PMLC task force has been succeeded by the Systems and Architecture task force.
Resources curated for this task force include:
- The Opportunities and Challenges for Next Generation Computing white paper
- Challenges to Keeping the Computer Industry Centered in the US white paper (draft)
- The 21st Century Computer Architecture in 2012 white paper
- The Future of Computing Performance: Game Over or Next Level? white paper
- Nanotechnology-Inspired Information Processing Systems workshop report
- Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond workshop report
Workshops related to this task force include:
- Nanotechnology-Inspired Information Processing Systems workshop
- Extreme Scale Design Automation workshop series
- 2025 Roundtable