Cross-Layer Reliability (RELXLAYER) First Meeting
March 26-27, 2009
Intel Santa Clara
Santa Clara, CA, United States
2011 and Earlier, 2011 and Prior Events, Visioning Activities, Workshop
The Cross-layer Reliability (RelXLayer) visioning process addresses the fact that we will no longer be able to reliably design or manufacture fault-free hardware systems. As the critical dimensions of devices, such as transistors and wires, used to implement computer systems shrink to only a few nanometers, rates of transient faults, permanent defects, and variation between devices on the same die are expected to increase to the point where today’s fault-tolerant approaches will no longer be practical. Instead, computer systems will need to adopt a model in which each layer in the abstraction hierarchy – applications, O/S, architecture, circuits – is prepared for the layer below to transmit bad data and in which all of the layers in the hierarchy cooperate to deliver correct operation in spite of faults, variations, and other effects. Exacerbating this challenge is the need to continually reduce net energy per operation while providing this protection.
RelXLayer draws participants from the broader computer research community to nurture a vision for a multi-level approach to reliability, generating a clear picture of the challenges and opportunities offered in multi-level reliability approaches. To foster this community, the group held three workshops to engage researchers and practitioners aimed at addressing this abstraction hierarchy and initiating cross-layer discussions.
March 26, 2009 (Thursday)
|09:30 AM||Present proposal|
|10:30 AM||Immediate (short) questions|
|11:00 AM||Full group discussion of case/questions|
|01:30 PM||Breakout 1 (6 groups, 1 per question)|
|02:45 PM||Breakout 2 (6 groups, chance to attend different one)|
|04:00 PM||Missing question open microphone|
|05:00 PM||End Day 1|
March 27, 2009 (Friday)
|08:00 AM||Breakout groups finish assembling materials for presentation|
|09:00 AM||Present from Q1--Q3 group|
|10:45 AM||Present from Q4--Q6 group|
|12:15 PM||Pickup lunch|
|12:30 PM||Missing Q presentations|
|01:30 PM||End Meeting|
Date: March 26-27, 2009
Location: Intel Santa Clara
Intel Corporation’s Robert Noyce Building, Main Lobby
2200 Mission College Boulevard
Santa Clara, California 95052-8119
(gif, BROKEN LINK)
From Highway 101: Take the Montague Expressway exit. Turn left on Mission College Boulevard. Turn left into the Intel Corporation campus. Visitor parking is on the right. Enter the museum to the left of the main lobby of the Robert Noyce Building.
From Highway 880: Take the Montague Expressway exit west. Turn right on Mission College Boulevard. Turn left into the Intel Corporation campus. Visitor parking is on the right. Enter the museum to the left of the main lobby of the Robert Noyce Building.
From Highway 280: Exit on Highway 880 north to Highway 101 north. Take the Montague Expressway exit. Turn left on Mission College Boulevard. Turn left into the Intel Corporation campus. Visitor parking is on the right. Enter the museum through the main lobby of the Robert Noyce Building.
Passenger Drop-Off: Buses may discharge passengers in front of the Robert Noyce Building. Buses may not park in front of the building or in the visitor parking lot. Bus drivers may park in the Freedom Circle parking lot shown on the map above.
Public Transportation: For information on public transportation resources, contact Valley Transportation Authority at (408) 321-2300 or check the Web site at http://www.vta.org.
Accommodations can be made at the Hilton Santa Clara, located at:
Hilton Santa Clara
4949 Great America Parkway
Santa Clara, California 95054
A rate of $189/night has been arranged for meeting participants.