Physics & Engineering Issues in Adiabatic/Reversible Classical Computing
October 5-9, 2020
Virtual Event
Zoom Meeting
Event Contact
Ann Drobnis
adrobnis@cra.org
2022530381
Event Type
2020 Events, 2020 Visioning Activities, Workshop
Event Category
Tags
computer architecture, computer hardware, reversible computing
The Computing Community Consortium (CCC) held a virtual workshop the week of Oct. 5-9 (with a virtual reception on Friday, Oct. 2) to address the physics & engineering challenges in adiabatic/ reversible classical computing. This workshop gathered the research community in this field to lay a common foundation of existing state-of-the-art knowledge and work together to prepare a comprehensive workshop report that can make the case for a major new initiative effectively to federal-level decision-makers.
Learn more about the motivation for the workshop below and watch recorded plenary talks from the workshop here.
It has become widely recognized that today’s approach to general digital computation, which is based on standard combinational and sequential digital architectures constructed out of standard (irreversible) Boolean logic elements implemented using CMOS (complementary metal/oxide/semiconductor) transistor technology, is approaching fundamental physical limits to further improvements on its energy efficiency and power-limited performance. The final (2015) edition of the International Technology Roadmap for Semiconductors (ITRS), as well as recent editions of its successor roadmap, the International Roadmap for Devices and Systems (IRDS), suggest that a practical limit will be reached by around the year 2030. By the end of the CMOS roadmap, logic signal energies at the gate of a minimum-sized transistor simply cannot decrease much further without running afoul of fundamental limits on efficiency and stability arising from thermal fluctuations. Even moving to “Beyond CMOS” switching devices cannot improve this situation very much, since the same fundamental thermodynamic limits still apply.
Thus, there is an increasing need to explore new fundamental paradigms for the engineering implementation of general computing systems (at all scales from tiny embedded devices to large-scale supercomputers and data centers) in search of novel concepts for computation that can transcend the above limits that are inherent to the traditional irreversible digital paradigm. The space of ideas that have been considered include a variety of concepts for “physical” computing (computing that leverages fundamental physics to do computing in a more direct way than in the traditional digital paradigm), including various analog and stochastic computing concepts, as well as quantum computing (for problems amenable to quantum speedups).
In January 2019, a CCC workshop on “Thermodynamic Computing” (TDC) was held specifically to explore the space of new computing paradigms inspired by the application of the principles of thermodynamics (and in particular, the modern non-equilibrium/stochastic approaches to thermodynamics). During the breakout sessions of the TDC workshop, Michael Frank (one of the organizers of this Reversible Computing workshop) proposed a related new “priority research direction” on “Physics and Engineering of Reversible Computing Hardware”[1]. As discussed in the resulting TDC workshop report, reversible computing can be considered to be the historically first conceptualization of thermodynamic computing, having first been considered in as early as 1961 by Rolf Landauer [2].
However, despite the broad applicability of reversible computing, and its rather conservative nature relative to the wider playing field of alternative computing schemes, the mainstream computing industry still views reversible computing as constituting an extremely radical departure from the way things are done today. There are a substantial number of important questions about basic physical science issues pertaining to reversible computing that still need to be explored. These are in the nature of quite fundamental research problems that, if they were investigated in more depth and solved effectively, could result in revolutionary improvements in the basic practical characteristics (speed, power, size, cost) of the primitive functional elements of a reversible machine, as well as the higher-level circuits and systems built out of these.
Thus, we view the basic science and engineering of reversible computers as being currently an extremely ripe area of focus for future large-scale federal research initiatives, for the following reasons:
- The reversible computing field is absolutely necessary for there to be any hope of advancing ordinary general digital computing beyond the energy-efficiency limits that apply to the conventional computing paradigm, which will definitely be reached in the foreseeable future;
- There is a range of important foundational physical science research in the reversible computing field that could have potential revolutionary impact, that still needs to be done;
- This field has so far been too forwards-looking for industry to invest in directly, although at least one major industrial research lab is presently considering starting up a project to investigate the limits of computing, including reversible computing.
- There has not yet been any major U.S. Federal research initiative that has focused on this field. We only know of two, relatively small Federal programs that are active in this field currently:
- The “Adiabatic/Reversible Logic Test Chip” STTR program sponsored by AFRL [3]; so far only two university performers (Notre Dame and University of Kentucky) have been sponsored under this program;
- The Army Research Office’s Advanced Computing Initiative (ACI) [4] mentioned reversible computing as an area of interest, and we know that there has been at least one award for reversible computing issued under that program (to Sandia).
This workshop gathered the research community in this field to lay a common foundation of existing state-of-the-art knowledge, and work together to prepare a comprehensive workshop report that can make the case for a major new initiative effectively to federal level decision-makers. Workshop attendance was by invitation only.
[1] M. P. Frank, “Priority Research Direction: Physics & Engineering of Reversible Computing Hardware,” January 2019. [Online]. Available: https://cfwebprod.sandia.gov/cfdocs/CompResearch/docs/Frank_Reversible_Computing_2v1.pdf. [Accessed 20 September 2019].
[2] R. Landauer, “Irreversibility and Heat Generation in the Computing Process,” IBM Journal of Research and Development, vol. 5, no. 3, pp. 183-191, 1961.
[3] A. C. Pineda, “Adiabatic/Reversible Logic Test Chip,” 20 April 2018. [Online]. Available: https://www.sbir.gov/sbirsearch/detail/1482545. [Accessed 20 September 2019].
[4] J. M. Coyle, “Broad Agency Announcement for Department of Defense Advanced Computing Initiative (ACI),” February 2019. [Online]. Available: https://www.arl.army.mil/www/pages/8/ARO%20NSA%20BAA%20-%20final%20to%20post%20secure%20v2.pdf. [Accessed 20 September 2019].
October 2, 2020 (Friday)
Welcome Reception
3:00 PM PDT – 5 PM PDT |
October 5, 2020 (Monday)
Workshop Introduction
8:30 AM – 9:20 AM PDT |
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Intro. to Physics Session
9:20 AM – 10:00 AM PDT
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Plenary Session 1
10:00 AM – 10:20 AM PDT
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BREAK
10:20 AM – 10:50 AM PDT |
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Plenary Session 2
10:50 AM – 11:50 AM PDT
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Panel/Q&A
11:50 AM – 12:10 PM PDT |
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BREAK
12:10 PM – 12:40 PM PDT |
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Physics Breakout
12:40 PM – 2:40 PM PDT Slides: |
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End Day 1
2:40 PM PDT |
October 6, 2020 (Tuesday)
Keynote
8:50 AM – 9:20 AM PDT
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Plenary Session 3
9:20 AM – 10:20 AM PDT
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BREAK
10:20 AM – 10:50 AM PDT |
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Plenary Session 4
10:50 AM – 11:50 AM PDT
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Panel/Q&A
11:50 AM – 12:10 PM PDT |
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BREAK
12:10 PM – 12:40 PM PDT |
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Technology Breakout
12:40 PM – 2:40 PM PDT |
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End Day 2
2:40 PM PDT |
October 7, 2020 (Wednesday)
Plenary Session 5
8:30 AM – 10:20 AM PDT
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BREAK
10:20 AM – 10:50 AM PDT |
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Plenary Session 6
10:50 AM – 11:50 AM PDT
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Panel/Q&A
11:50 AM – 12:10 PM PDT |
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BREAK
12:10 PM – 12:40 PM PDT |
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Architecture & High-Level (Tools / Algorithms / Systems / Apps.) Breakouts
12:40 PM – 3:10 PM PDT Architecture Breakout |
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End Day 3
3:10 PM PDT |
October 8, 2020 (Thursday)
Day 4 Intro
9:00 AM – 9:20 AM PDT |
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Outbriefs from Breakouts
9:20 AM – 10:20 AM PDT |
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BREAK
10:20 AM – 10:50 AM PDT |
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Concordance Discussion #1
10:50 AM – 12:10 PM PDT |
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BREAK
12:10 PM – 12:40 PM PDT |
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Second-Round Breakouts
12:40 PM – 3:10 PM PDT |
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End Day 4
3:10 PM PDT |
October 9, 2020 (Friday)
Day 5 Intro
9:00 AM – 9:20 AM PDT |
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Outbrief from Breakouts
9:20 AM – 10:20 AM PDT |
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BREAK
10:20 AM – 10:50 AM PDT |
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Concordance Discussion #2
10:50 AM – 12:10 AM PDT |
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BREAK
12:10 PM – 12:40 PM PDT |
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Final Breakout
12:40 PM – 1:40 PM PDT |
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BREAK
1:40 PM – 2:10 PM |
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Final Concordance
2:10 PM – 4:10 PM PDT |
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End Day 5
4:10 PM PDT |
Workshop Organizers and Program Committee:
Michael (Mike) Frank, Sandia National Labs |
Tom Conte, Georgia Tech |
Erik DeBenedictis, Zettaflops, LLC |
Jayson Lynch, Massachusetts Institute of Technology |
Karpur Shukla, Brown University |
Robert Wille, Johannes Kepler University Linz |
With Support From CCC System and Architecture Task Force Members:
Sujata Banerjee, VMware |
Mark Hill, University of Wisconsin, Madison |
Due to the COVID-19 pandemic this workshop will take place virtually. Workshop participants will be invited to join the workshop based on their submission of relevant position paper (see more in the Application tab). While virtual, we expect participants to fully participate in all days of the workshop.
For this workshop we request position papers of no more than two pages in length. Please consider addressing questions like:
- What is the sub-problem or problems that you think most needs to be tackled and why?
- Are there reasons the problem has become more important?
- What insights lead you to hypothesize that better solutions are possible now?
- What research program or plan do you foresee as needed to achieve success
Topics of interest include, but are not limited to:
- Physics-based models of reversible computing.
- Physical limits of reversible computing (including fundamental limits).
- Device technologies for reversible computing.
- Circuit design techniques for reversible computing.
- Design tools / hardware description languages for reversible machines.
- Processing architectures for reversible computing (including hybrid approaches).
- Programming models for (partly/fully) reversible architectures.
- Systems engineering for reversible computing systems (including scaling analyses, design tradeoffs).
- Asymptotically efficient reversible algorithms for important problems.
- Applications of (energy efficient) reversible computing.
Topics out of scope include:
- Work that deals entirely at the level of abstract operation sequences (e.g. ccNOT operations), without attention being paid to how these map to practical hardware architectures/engineering implementations.
- Any topics in quantum computing that do not also have relevance to classical reversible computing.
- Unconventional computing paradigms that are unrelated to reversible computing.
- Applications of logically reversible computing (e.g., for transaction rollback) that do not require approaching a physically reversible implementation.
- Any abstract theory topics not having any clear/direct relevance to practical applications, engineering, or systems.
If you are interested in participating in the workshop, please submit your position paper here no later than 11:59 PM PT on August 21st. We will notify selected participants by August 31st.
Authors of position papers may be asked to record video presentations about their paper to be made available during/after the workshop. While virtual, we expect participants to fully participate in all days of the workshop. A specific agenda with times is forthcoming.