What do multiprocessors, zebras, and qubits have in common? The field of computer architecture sits at the hardware-software interface, and computer architects play the role of mediating between technology trends emanating “from below” and application trends influencing the field “from above.” Over the 30 years since I began graduate school, my computer architecture research has explored many topics, but the ongoing theme has been attention to how technology and application trends and constraints influence hardware and system design, particularly at the hardware-software interface.
A technology trend of particular note today is the deceleration of Moore’s Law and Dennard scaling. Previously semiconductor scaling enabled decades of exponential improvements in semiconductor density, performance, and power efficiency, but we are now reaching fundamental physical limits; one consequence has been the increasing importance of accounting for power constraints throughout the system design process. Today’s computer systems’ power challenges affect not only mobile devices (where battery life is a clear concern) but also all the way up to large-scale data centers that consume tens of megawatts of power, akin to a small city.
Over the years, my research has explored many different aspects of power-aware computer architecture, including both power-saving and power-measurement techniques, and widely disseminated software and tools. Our work on the Wattch architecture-level power simulator allowed many researchers to experiment with power-efficient architecture techniques. At a different level, other work from our group studied methods for optimizing the routing of internet requests to data centers in ways that could minimize total energy cost or maximize the exploitation of green energy for a given global-scale internet service. One key aspect of all this work has been to establish the role of computer architects and early-stage design approaches in power issues that previously were mostly considered to be the domain of circuits and device-level work.
Another line of my work was motivated by the desire to do a top-to-bottom, application-to-hardware exploration of power-efficiency issues in mobile systems. Our collaboration with biologists interested in improving the state-of-the-art in wildlife tracking led my group to embark on researching mobile sensor networks. This work culminated in the design and real-world deployment of ZebraNet, a peer-to-peer mobile network of GPS-based tracking collars for zebras in the Laikipia region of Kenya. In addition to greatly improving the spatiotemporal detail of wildlife data available in that region, this work was noteworthy in establishing the use of mobile sensors and delay-tolerant networking (DTN) techniques for energy-efficient large-scale environmental sensing. As a related project in the following years, we adapted these ideas for other applications, including designing and deploying a vehicular DTN system for providing low-cost internet access to disconnected rural villages in northern Nicaragua. That work, in turn, led us, working with collaborators from Rutgers University and AT&T, to study broader techniques for mobile opportunistic sensing, including methods for using coarse-grained and differentially private cellphone usage data to characterize labor and commute patterns for large regions, and to compare major cities such as New York, Los Angeles, and San Francisco.
In my most recent work, the trends and goals continue to evolve, but the focus at the hardware-software interface remains. One aspect of my current work is building tools and techniques to automatically verify the correctness of memory consistency models (MCMs) in modern computer systems. MCMs specify the rules by which memory accesses can be reordered for performance purposes in parallel systems, and today’s complex, heterogeneously parallel systems make MCMs simultaneously crucially important, and also very hard to ascertain the correctness of. Our automatic verification tools mitigate the complexity of building correct hardware, and of mapping properly to that hardware from high-level languages through compiler and operating system layers.
Finally, a thread of my work looks beyond current CMOS-based classical computing approaches and toward a world where quantum computing (QC) might soon play an important role. With QC hardware rapidly improving, my QC work explores compilation, scheduling, and parallelization techniques that help optimize the path from high-level QC algorithms to lower-level QC devices. In the process, our work allows designers to explore tradeoffs in how QC systems are organized and what error-correction methods make the most sense.
Overall, across these different threads of research, the fundamental vision remains one that recognizes the central role of computer architecture as a mediator of applications and technology trends. Taking this broad view of computer architecture and its role in overall hardware and software systems research, my work has given me a huge variety of topics and challenges to attack.
About the Author
Margaret Martonosi is the Hugh Trumbull Adams ’35 Professor of Computer Science at Princeton University, where she has been a faculty member since 1994. Martonosi holds affiliated appointments in Princeton’s Electrical Engineering Department, its Center for Information Technology Policy, its Environmental Institute, and its Andlinger Center for Energy and the Environment. From 2005-2007, she served as associate dean for academic affairs for the School of Engineering and Applied Science. In addition to her primary position at Princeton, she is an Andrew Dickson White Visiting Professor-At-Large at Cornell University. From 2015 to 2017, she did international technology policy as a Jefferson Science Fellow within the U. S. Department of State.
Martonosi is a fellow of both IEEE and ACM. Her major awards include Princeton University’s 2010 Graduate Mentoring Award, the Anita Borg Institute’s 2013 Technical Leadership Award, and test-of-time paper awards from ISCA and ACM SIGMOBILE. Martonosi co-chairs the NSF CISE Advisory Committee, has served on the board of directors of the Computing Research Association (CRA) since 2009, and will be co-chairing CRA-Women beginning in October, 2017.